A data-science team is iterating on a predictive-maintenance model that will run on an existing ARM Cortex-M7 microcontroller already installed in thousands of factory machines. The design specification for the edge deployment requires that average inference latency must stay below 10 ms and no more than 512 KB of total RAM may be used; the MCU lacks a floating-point unit. The hardware cannot be replaced or upgraded for at least five years.
The first prototype is a 1-D CNN with 500,000 parameters stored as 32-bit floats. On the target device it consumes about 2 MB of RAM and each prediction takes roughly 90 ms, although prediction accuracy meets business requirements.
Which design-iteration action should the team prioritize next to satisfy the hardware and timing constraints without purchasing new hardware?
Retrain the CNN using quantization-aware techniques so that weights and activations are stored as 8-bit integers.
Increase the kernel size and number of filters in every convolutional layer to improve feature extraction.
Raise the inference batch size from 1 to 32 to maximize throughput on the microcontroller.
Replace the CNN with an LSTM architecture that uses twice as many hidden units to model temporal sequences.
Converting both weights and activations from 32-bit floating point to 8-bit integers through quantization-aware training (or an equivalent post-training integer quantization workflow) typically reduces model size by a fourfold factor and enables execution with integer arithmetic. This directly lowers RAM usage to approximately 500 KB (from 2 MB), satisfying the 512 KB limit. It also accelerates inference on MCUs that lack an FPU, often yielding two- to fourfold speed-ups. The other choices either increase model complexity, enlarge intermediate tensors, or multiply per-inference work-each would further violate the existing memory or latency specifications rather than mitigate them.
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