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CPU Architectures and Socket Types Flashcards
| Front | Back |
| ARM instruction set architecture | Reduced Instruction Set Computing used in mobile and embedded devices |
| BGA socket type | Ball Grid Array permanently soldered to the motherboard |
| CISC vs RISC | CISC has complex instructions while RISC has simple fixed-length instructions |
| CPU core | Independent processing unit within a CPU capable of executing tasks |
| CPU multiplier | Factor that multiplies the base clock to determine the CPU frequency |
| CPU thread | Virtualized division of a core that handles instruction streams concurrently |
| Difference between LGA and PGA | LGA has pins on the socket while PGA has pins on the CPU |
| Hyper-threading | Intel technology allowing a single core to handle two threads simultaneously |
| L1 cache | Smallest and fastest cache located closest to the CPU core |
| L2 cache | Medium size cache that balances speed and capacity |
| L3 cache | Largest cache shared among multiple cores |
| LGA socket type | Land Grid Array where pins are on the motherboard |
| Overclocking | Running a CPU at a higher frequency than its base clock |
| PGA socket type | Pin Grid Array where pins are on the CPU |
| Turbo Boost | Technology that temporarily increases CPU frequency above base clock |
| x86 instruction set architecture | Complex Instruction Set Computing used by Intel and AMD |
Front
Hyper-threading
Click the card to flip
Back
Intel technology allowing a single core to handle two threads simultaneously
Front
L2 cache
Back
Medium size cache that balances speed and capacity
Front
CISC vs RISC
Back
CISC has complex instructions while RISC has simple fixed-length instructions
Front
Overclocking
Back
Running a CPU at a higher frequency than its base clock
Front
Difference between LGA and PGA
Back
LGA has pins on the socket while PGA has pins on the CPU
Front
CPU thread
Back
Virtualized division of a core that handles instruction streams concurrently
Front
BGA socket type
Back
Ball Grid Array permanently soldered to the motherboard
Front
L3 cache
Back
Largest cache shared among multiple cores
Front
CPU core
Back
Independent processing unit within a CPU capable of executing tasks
Front
LGA socket type
Back
Land Grid Array where pins are on the motherboard
Front
L1 cache
Back
Smallest and fastest cache located closest to the CPU core
Front
Turbo Boost
Back
Technology that temporarily increases CPU frequency above base clock
Front
x86 instruction set architecture
Back
Complex Instruction Set Computing used by Intel and AMD
Front
CPU multiplier
Back
Factor that multiplies the base clock to determine the CPU frequency
Front
ARM instruction set architecture
Back
Reduced Instruction Set Computing used in mobile and embedded devices
Front
PGA socket type
Back
Pin Grid Array where pins are on the CPU
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Covers major CPU socket standards (LGA, PGA, BGA), instruction set architectures (x86, ARM), core vs. thread concepts, cache levels and overclocking basics.